Cadence Signs Definitive Agreement to Acquire Verplex; Electronic Design Leader Enhances RTL-GDSII Flow with Market-Leading Formal Verification Technology

SAN JOSE, Calif.--(BUSINESS WIRE)--July 14, 2003--Cadence Design Systems Inc. (NYSE:CDN) today announced it has signed a definitive agreement to acquire Milpitas, Calif.-based Verplex Systems, Inc., the acknowledged leader in formal verification electronic design software. The Verplex technology will help Cadence provide customers with formal verification that offers independent verification with best-in-class speed, capacity and debug environment to automate the RTL-GDSII flow.

Cadence expects to close the transaction in the third quarter of this year. This acquisition is a key milestone in the company's ongoing platform strategy to provide customers with a complete design-to-volume flow. Cadence will incorporate Verplex's formal verification technology into the Cadence(R) Encounter(R) digital IC platform's nanometer implementation flow, the industry's route to big, fast chips, and Cadence's market-leading Cadence Incisive(TM) verification platform. Cadence also will continue to support Verplex products in alternative flows.

"The next step in our overall strategy, Verplex is an integral part of the fabric of technologies required by power users and the most aggressive designers, and it has, in a very short time, become the standard for designing high-performance chips," said Ray Bingham, president and CEO of Cadence. "This technology has rapidly won over customers to capture the top half of the market -- leaders in the semiconductor industry -- and now gives us a significant edge in helping customers solve their most difficult problems. Verplex expands Cadence's leadership, has no overlapping technology with existing Cadence technology, enabling independent verification, and brings in a world-class technology team and leaders."

A recent independent study indicated that more than half of all chips required one or more re-spins, and that functional errors were found in 74 percent of these re-spins. Verplex's solution addresses this challenge by detecting functional differences between successive revisions of a chip design from RTL to GDSII, and includes unique datapath, digital custom and memory verification capabilities.

"The addition of Verplex's leading technology complements the Cadence Encounter and Incisive platforms' superior prototyping, routing, signal integrity, synthesis and single-kernel verification capabilities," said Ping Chao, senior vice president and general manager at Cadence. "Independent formal verification is an integral component of a high-end nanometer chip design flow. It will enable customers to handle verification of even bigger, faster chips."

"The Verplex team is excited to be part of Cadence during this period of challenge and growth," said Michael Chang, president and CEO of Verplex. "Verplex's products are rated No. 1 in speed, capacity and usability. Our companies' technologies are highly complementary and will extend Cadence's ability to provide technology to design big, fast chips by adding independent formal verification to its nanometer IC implementation and verification flows."

Design closure is achieved when an implemented design meets its performance specifications. A logically correct Register Transfer Level (RTL) design, or golden RTL, still undergoes massive transformations and iterations before final layout. Each step in this process can introduce logical inconsistencies, or bugs. As IC designs grow in size and complexity, the importance of independent formal verification grows.

"Agilent Technologies has successfully leveraged leading-edge technology from both Cadence and Verplex to meet our aggressive product cycles and customers' turn-around requirements," said Richard Nash, Director of Engineering for Agilent's ASIC Products Division. "We believe that the combination of these solutions will provide even better results and will further improve our ability to ensure schedule predictability and time-to-market in our nanometer design flow."

"We find that formal verification is mandatory technology for a successful automated design flow," said Shardul Kazi, vice president of the TX RISC Business Unit at Toshiba America Electronic Components, Inc. "Cadence tools meet our nanometer design needs for creating multi-million gate Application Specific Standard Products and Custom System-on-Chip designs. By bringing the Verplex technology into the Cadence solution, we look forward to even higher-quality results and improved time-to-market."

A roadmap for the incorporation of Verplex's products is currently under development. This will include Conformal LEC logic equivalence checker, Conformal LTX logic transistor extractor, Conformal FPGA equivalence checker, Conformal LVR layout versus RTL, Conformal MEM memory equivalence checker, Conformal Datapath circuitry checker, and BlackTie assertion-based verification.

About Verplex

Verplex Systems Inc. is an electronic design automation (EDA) company focusing on delivery of the highest speed, highest capacity and easiest to use formal verification products for complex system-on-chip (SOC) design. Founded in 1997, it is privately held and funded by leading venture capital firms. Corporate headquarters is located at 300 Montague Expressway, Suite 100, Milpitas, Calif. 95035. Telephone: 408/586-0300. Facsimile: 408/586-0230. Email: info@verplex.com. Online information is found at its Web Site: http://www.verplex.com.

About Cadence

Cadence is the world's leader in electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,200 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.

Except for historical information, the matters discussed in this release contain forward-looking statements, including, without limitation, statements related to beliefs and expectations regarding the acquisition of Verplex and other recent acquisitions; expectations and intentions regarding products and technologies; and beliefs and expectations regarding Cadence's employees, business, competitors and customers. These statements are based on current expectations or beliefs and are subject to factors and uncertainties that could cause actual results to differ materially from those described in the forward-looking statements, including without limitation, the successful integration of Verplex's employees and technologies; the rapid pace of technological change in the electronics and semiconductor industries; fluctuations in the demand for Cadence's products, services and solutions; possible development or marketing delays relating to product offerings; and the introduction of new products by competitors or the entry of new competitors into the markets for Cadence's products. For a detailed discussion of these and other cautionary statements, please refer to Cadence's most recent filings with the Securities and Exchange Commission. Cadence does not undertake any obligation to update forward-looking statements to reflect events or circumstances occurring after the date of this press release.

Cadence, the Cadence logo, Incisive and Encounter are trademarks or registered trademarks of Cadence Design Systems Inc. All others are property of their respective companies.

CONTACT: Cadence Design Systems, Inc.
             Judy Erkanat, 408/894-2302
             jerkanat@cadence.com